System and method for optimizing clock speed generation in a computer

ABSTRACT

The present invention relates to a method of reducing a clock speed of a host bus to extend battery life and its operating time when a battery is supplying electric energy for a portable computer. A bus clock controlling apparatus according to the present invention includes power mode detecting means detecting a current power mode, the power mode indicative of which power source supplies the portable computer with electric energy; and clock adjusting means adjusting frequency of an applied clock from a clock generator based on the detected power mode by said power mode detecting means, and applying the frequency-adjusted clock to one or more controlling devices. Due to this invention, an electric energy stored in a battery equipped in a portable computer is saved, as a result, the battery life is extended.

This application is a reissue patent application of U.S. Pat. No.7,096,373, which is issued from U.S. application Ser. No. 10/003,345.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus and a method ofcontrolling clock frequency generation, and more particularly, to anapparatus and a method for a portable device.

2. Background of the Related Art

In general, a portable device such as a notebook computer can besupplied with its necessary electric energy either by a battery or an ACpower line. However, because battery capacity is limited, a notebookcannot be used for more than a few hours if its power is supplied fromthe battery.

FIG. 1 is a simplified block diagram of a related art notebook. Thenotebook of FIG. 1 comprises a CPU 11 conducting ordinary well-knownoperations and functions; a bridge controller 12 conducting bothassistant operations of the CPU 11 and management of memories, a videoport, a bus, etc.; a video processor 13 for processing video data andoutputting the processed data for video presentation; and a clockgenerator 10 providing a 100 MHz clock signal 1 for the CPU 11 and thebridge controller 12, and a 66 MHz clock signal 2 for the videoprocessor 13.

A PLL (Phase Lock Loop) circuit 110 is embedded in the CPU 11. The PLLcircuit 110 multiplies the 100 MHz clock from the clock generator 10differently based on a current power supplying mode. For example, thePLL circuit 110 multiplies the 100 MHz clock 1 by a factor of six toproduce a 600 MHz internal clock if an AC power mode (PWR mode) isdetected, and it multiplies the 100 MHz clock 1 by a factor of five toproduce a 500 MHz clock if a battery power mode is detected.

Because power consumption of a CPU 11 is proportional to the speed of aclock driving the CPU 11, if a 500 MHz internal clock is used in abattery supplying mode, processing speed is lowered and powerdissipation is decreased in comparison with a 600 MHz internal clock.Therefore, battery life is extended.

However, in a related portable computer, a host bus 3 to which both aCPU 11 and a bridge controller 12 are connected is driven by a bus clockto bridge controller 12 whose speed is fixed regardless of powersupplying mode. Therefore, power saving in a battery supplying mode isless effective.

The above references are incorporated by reference herein whereappropriate for appropriate teachings of additional or alternativedetails, features and/or technical background.

SUMMARY OF THE INVENTION

An object of the invention is to solve at least the above problemsand/or disadvantages and to provide at least the advantages describedhereinafter.

Another object of the present invention is to provide a method ofreducing clock speed of a bus in order to extend battery suppliable timelonger when electric energy is fed to a portable computer such as anotebook from an equipped battery.

In order to achieve at least the above-described objects of the presentinvention in a whole or in part, there is provided a portable devicehaving a CPU and a bridge controller operating in one of AC power modeor battery power mode, wherein the improvement includes a clockgenerator generating a first clock signal for the CPU and a second clocksignal for the bridge controller, wherein first and second clock signalsare two distinct clock signals outputted by the clock generator and havedifferent frequencies.

To further achieve at least the above-described objects of the presentinvention in a whole or in parts, there is provided a portable devicehaving a CPU and a bridge controller, wherein the improvement includes aclock generator generating a first clock signal, and a clock adjustoroperating in one of AC power mode or battery power mode, said clockadjustor generating a second clock signal for the CPU and a third clocksignal for the bridge controller, wherein the second and third clocksignals are two distinct clock signals outputted by the clock adjustorand have different frequencies.

To further achieve at least the above-described objects of the presentinvention in a whole or in parts, there is provided a method foroptimizing clock speed generation, including receiving a base clocksignal, multiplying the base clock signal by a first factor to produce afirst higher frequency clock signal, wherein the first higher frequencyclock signal is phase-locked with the base clock signal, receiving apower mode signal indicating either an AC or a battery source, andselectively outputting the first higher frequency clock signal to afirst device when the AC source is indicated and outputting the baseclock signal to the first device when the battery source is indicated.

Additional advantages, objects, and features of the invention will beset forth in part in the description which follows and in part willbecome apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theinvention. The objects and advantages of the invention may be realizedand attained as particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in detail with reference to thefollowing drawings in which like reference numerals refer to likeelements wherein:

FIG. 1 is a partial block diagram of a related art computer;

FIG. 2 is a partial block diagram of a portable computer in which a busclock controlling apparatus in accordance with a preferred embodiment ofthe present invention is embedded;

FIG. 3 is a detailed block diagram of the PLL circuit built in acontrolling device according to the embodiment of FIG. 2;

FIG. 4 is a block diagram of a portable computer in which another busclock controlling apparatus in accordance with a preferred embodimentthe present invention is embedded; and

FIG. 5 is a detailed block diagram of the PLL block applying each clockto each device according to the embodiment of FIG. 4.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In order that the invention may be fully understood, preferredembodiments thereof will now be described with reference to theaccompanying drawings.

FIG. 2 is a block diagram of a portable computer in which a bus clockcontrolling apparatus in accordance with the present invention isembedded. The portable computer of FIG. 2 includes a CPU 11, a bridgecontroller 22, and a video processor 23. The portable computer of FIG. 2further comprises a clock generator 20 which may provide CPU 11, bridgecontroller 22 and video processor 23 with necessary clock signals.

The clock generator 20 may provide the CPU 11 with a 100 MHz CPU clocksignals 101, the bridge controller 22 with a 66.7 MHz host clock signals102 (lower in frequency than the 100 MHz CPU clock 101), and the videoprocessor 23 with a 33.33 MHz clock signal 103 (lower in frequency thana conventional 66 MHz AGP clock).

A PLL circuit 210 may be included in the CPU 11. As aforementioned, thePLL circuit 110 may multiply the 100 MHz CPU clock 101 from the clockgenerator 20 selectively based on the current power supplying mode. Forexample, the PLL circuit 110 may multiply the frequency of a 100 MHzclock 101 by six if an external AC power is fed, and it may multiply thefrequency by five if a battery is supplying necessary electric energy.

In addition, another PLL circuit 220 may be embedded in the bridgecontroller 22. The PLL circuit 220 may multiply the frequency of the66.7 MHz host clock 102 from the clock generator 20 by one and a half toproduce a 100 MHz PCI bus clock in an AC power supplying mode, and mayuse the 66.7 MHz host clock 102 as it is without frequencymultiplication in a battery supplying mode.

FIG. 3 is a detailed block diagram of the PLL circuit 220. The PLLcircuit 220 may include a phase comparator 221 outputting a DC voltageproportional to the phase difference between the 66.7 MHz host clock 102and a divided internal oscillating clock; a voltage controlledoscillator (VCO) 222 generating the internal oscillating clock of about400 MHz whose frequency varies in proportion to the level of the DCvoltage applied from the phase comparator 221; a ⅙ frequency divider 223dividing the 400 MHz internal oscillating clock by 6 to produce a 66.7MHz clock; a ¼ frequency divider 224 dividing the 400 MHz internal clockby 4 to produce a 100 MHz clock; and a switch 225 selecting the inputted66.7 MHz host clock 102 or the divided 100 MHz clock 102a in accordancewith the power supplying mode to output a host bus clock or to use it asan internal operation clock.

The PLL comparator 221 may output a DC signal to increase or decreasethe frequency of the internal oscillating clock generated by VCO 222 inproportion to the phase difference between two applied signals, so thatthe two applied signals become in phase exactly. Therefore, thefrequency of the internal oscillating clock may be six times as high asthat of the inputted 66.7 MHz host clock 102 while its phase is lockedwith the host clock 102. Accordingly, if the internal oscillating clockfrequency is divided by 4, a 100 MHz clock whose phase is locked withthe inputted host clock 102 may be produced and it can be used as a busclock of a host bus through the bridge controller 22.

The switch 225 may select the 66.7 MHz host clock 102 when the powersupplying mode is indicative of the battery mode, while it may selectthe 100 MHz clock 102a divided from the internal oscillating clock inthe external AC supplying mode. If a battery is supplying electricenergy, the above elements 221, 222, 223, and 224 need not be operative,thus it may be preferable to cut off power supply for them in that mode.

The video processor 23 may also include PLL circuit 230. The PLL circuit230 of the video processor 23 may multiply the 33.33 MHz clock from theclock generator 20 by two to produce a 66.7 MHz AGP video clock in ACpower supplying mode, and may use the 33.33 MHz clock without frequencymultiplication in battery supplying mode.

The structure of the PLL circuit 230 may be similar to that shown inFIG. 3 except for the frequency dividing ratio and other respects. Inthe PLL circuit 230 whose input frequency is 33.33 MHz, a 200MHz-oscillating clock may be generated from an internal clock generator(corresponding to the element 222 of FIG. 3), and a ⅓ frequency divider(corresponding to the element 224 of FIG. 3) may be used. In thisinstance a clock output by the 1/3 frequency divider is at a frequenceof 66.7 MHz.

In the portable computer configured as above, if a battery is supplyingelectric energy, the frequency of a bus clock provided to a host bus bythe bridge controller 22 may be decreased to 66.7 MHz from 100 MHz, andthe frequency of an internal clock used by the video processor 23 mayalso be decreased to 33.33 MHz from 66.7 MHz. This clock speed reductionresults in extension of battery life.

A detecting means, which outputs a signal indicating power supplyingmode after detecting which power source between an external AC power anda battery is supplied at present, can be integrated into the bridgecontroller 22 or may be implemented as a separate device.

FIG. 4 is a block diagram of a portable computer in which another busclock controlling apparatus in accordance with the present invention isembedded. In the block diagram of FIG. 4, PLL circuits for reducingclock speed in battery mode may not be included in the bridge controller32 and the video processor 33. Instead, a separate PLL block 40 may beincluded in the embodiment of FIG. 4. The PLL block 40, which can bemanufactured with a customized semiconductor such as an ASIC(Application Specific Integrated Circuit), may provide each element withrespective necessary clocks of mutually different frequency. A clockgenerator 30 may be further included in the embodiment of FIG. 4 tosupply the PLL block 40 with a basic clock 114 of 33.33 MHz.

However, a PLL circuit 110 for producing 600 MHz or 500 MHz bymultiplying 100 MHz differently may be embedded in the CPU 11 asmentioned above.

The frequency 33.33 MHz of the basic clock 114 applied to the PLL block40 from the clock generator 30 may be equal to the lowest among clockfrequencies the PLL block 40 provides in battery supplying mode. The PLLblock 40 may be configured as in FIG. 5 to supply all clocks, namely,100 MHz clock necessary to the CPU 11 regardless of power supplyingmode, and 33.33 MHz, 66.7 MHz and 100 MHz clocks which are selectivelyprovided to the bridge controller 32 and video processor 33 according topower supplying mode.

A phase comparator 421 of FIG. 5 may adjust the frequency of theapproximately 200 MHz oscillating clock of a VCO 422 in proportion to adetected phase difference between the 33.33 MHz clock 114 from clockgenerator 30 and a ⅙ divided clock from the 200 MHz oscillating clock.As a result, the phase of the 200 MHz oscillating clock may be lockedwith the applied 33.33 MHz clock 114 from clock generator 30.

In phase-locked state of the 200 MHz clock, a 100 MHz clock may beproduced from a ½ divider 423 dividing the 200 MHz clock by two, and66.7 MHz clock may also be produced from a ⅓ divider 425 dividing the200 MHz clock by three. Therefore, the 100 MHz clock 111 from the ½divider 423 may be applied to the CPU 11 at all times.

In the circuit of FIG. 5, switches 426a and 426b select ‘A’ terminals asinput if power supplying mode is indicative of external AC, so that the100 MHz clock is applied to the bridge controller 32 as host clock 112and the 66.7 MHz clock is applied to the video processor 33 as AGP clock113.

If electric power is fed from a battery, ‘B’ terminals are chosen;therefore, the host clock 112 and the AGP clock 113 become 66.7 MHz and33.33 MHz, respectively.

Accordingly, lower frequency clocks in battery mode than in AC mode maybe provided for corresponding devices, which means that powerconsumption is reduced when a battery is supplying necessary electricenergy.

In the embodiments of FIGS. 2 and 4, the output clocks of the clockgenerators 20 and 30 may be applied without regard to power supplyingmode. Furthermore, in the embodiments of FIGS. 2 and 4, clock frequencyadjusting means may be embedded in the CPU, bridge controller, and videoprocessors or implemented as a separate device.

As can be appreciated, based on the disclosure of the preferredembodiments, the output of the clock generators 20 and 30 of FIGS. 2 and4, respectively, may be applied without raising the frequency during thebattery power mode but increasing the clock frequency if an AC powermode is detected. Alternatively, the output of the clock generators 20and 30 may be applied without frequency adjustment in the AC power modebut decreasing the clock frequency if a battery power mode is detected.

In another embodiment, the clock frequency adjusting means may beintegrated into a clock generator 30. The clock frequency adjustingmeans mentioned here is a device which adjusts or maintains frequency ofan input clock based on which power source is feeding electric energy,and applies the frequency-adjusted or -maintained clock to externaldevices.

An alternative embodiment of the invention, the frequency adjustingmeans may be embedded in other combinations of the clock generator, PLLASIC, CPU, bridge controller, video processor, and/or other devices.

The bus clock controlling apparatus of a portable computer according tothe present invention reduces speed of a bus clock and a device clock inbattery mode. Therefore, electric energy stored in a battery is saved,extending battery life.

In addition, the present invention can be applied to a PCI bus for datacommunication among peripheral devices connected to the PCI bus byproviding the clock to another Bridge controller for a PCI bus in thesame way as for the host bus.

The foregoing embodiments and advantages are merely exemplary and arenot to be construed as limiting the present invention. The presentteaching can be readily applied to other types of apparatuses. Thedescription of the present invention is intended to be illustrative, andnot to limit the scope of the claims. Many alternatives, modifications,and variations will be apparent to those skilled in the art. In theclaims, means-plus-function clauses are intended to cover the structuresdescribed herein as performing the recited function and not onlystructural equivalents but also equivalent structures.

1. An apparatus having a CPU wherein the improvement comprises: a clockgenerator generating a first clock signal for the CPU, and a secondclock for the a bridge controller, wherein the first and second clocksignals are two distinct clock signals outputted by the clock generatorand have different frequencies; and athe bridge controller comprising alogic device for outputting the second clock signal adjusted based on apower source and independent of the first clock signal.
 2. The apparatusof claim 1, wherein the bridge controller controls a clock speed of abus connected between the CPU and the bridge controller for datacommunication among a plurality of peripheral devices of the apparatususing the adjusted second clock.
 3. The apparatus of claim 1, whereinthe power source is one of AC power mode and battery power mode.
 4. Theapparatus of claim 1, wherein the apparatus further includes a videoprocessor and the clock generator generates a third clock signal for thevideo processor, the third clock signal being distinct from the firstand second clock signals and having a different frequency than the firstand second clock signals.
 5. The apparatus of claim 4, wherein theimprovement further comprises a second logic device for receiving thethird clock signal and adjusting the third clock signal based on thepower source.
 6. The apparatus of claim 4, wherein the first clocksignal has a higher frequency than the second clock signal and thesecond clock signal has a higher frequency than the third clock signal,and wherein the bridge controller controls a clock speed of a bus fordata communication with the CPU.
 7. The apparatus of claim 1, whereinthe logic device increases a frequency of the second clock signal in anAC power mode and outputs the second clock signal without a frequencyadjustment in a battery power mode.
 8. The apparatus of claim 1, whereinthe logic device outputs the second clock signal in a battery power modewithout a frequency adjustment.
 9. The apparatus of claim 5, wherein thesecond logic device increases a frequency of the third clock signal inan AC power mode and outputs the third clock signal without a frequencyadjustment in a battery power mode.
 10. The apparatus of claim 5,wherein the second logic device outputs the third clock signal in abattery power mode without a frequency adjustment.
 11. The apparatus ofclaim 5, wherein the first logic is a phase locked loop (PLL) and thesecond logic device is a PLL.
 12. An apparatus having a CPU and a bridgecontroller, wherein the improvement comprises: a clock generatorgenerating a first clock signal; and a clock adjustor receiving thefirst clock signal and operating in a power source mode, said clockadjustor generating a second clock signal for the CPU and a third clocksignal for the bridge controller, wherein the second and third clocksignals are two distinct clock signals outputted by the clock adjustorand have frequencies that are independent of each other, wherein theapparatus further includes a video processor and the clock adjustorgenerates a fourth clock signal for the video processor, the fourthclock signal being distinct from the second and third clock signals andhaving a different frequency than the second and third clock signals.13. The apparatus of claim 12, wherein the bridge controller controls aclock speed of a bus for data communication among a plurality ofperipheral devices of the apparatus.
 14. The apparatus of claim 13,wherein the clock adjustor is a phase locked loop (PLL), and wherein thebus is a host bus.
 15. The apparatus of claim 12, wherein the CPUfurther comprises a phase locked loop (PLL) receiving the second clocksignal for the CPU and adjusting the second clock signal based on one ofAC power mode and battery power mode.
 16. The apparatus of claim 12,wherein the second clock signal has a higher frequency than the thirdclock signal and the third clock signal has a higher frequency than thefourth clock signal.
 17. The apparatus of claim 12, wherein the powersource is one of an AC power mode or a battery power mode.
 18. Theapparatus of claim 12, wherein the clock adjuster adjusts the thirdclock signal for the bridge controller based on the power source modeand independent of the second clock signal.
 19. The apparatus of claim12, wherein the second and third clock signals are independent of eachother in each of at least two power source modes, and wherein the secondclock signal includes at least two different frequencies selected inaccordance with the power source mode.
 20. A method for performing clockspeed generation, comprising: receiving a base clock signal; selectivelymultiplying the base clock signal by a first factor to produce a firsthigher frequency clock signal, and by a second factor to produce asecond higher frequency clock signal, wherein the first and secondhigher frequency clock signals are different and phase-locked with thebase clock signal; receiving a power mode signal; selectively outputtingthe first higher frequency clock signal to a first device and the secondhigher frequency clock signal to a second device based on the power modesignal, wherein the first device is a processor and the second device isa bridge controller; and generating a third higher frequency clocksignal for a video processor, wherein the third clock signal beingdistinct from the first and second clock signals and having a differentfrequency than the first and second clock signals.
 21. The method ofclaim 20, wherein the power mode signal is an AC power mode signal or abattery power mode signal and the second higher frequency clock signalis selectively output independent of the first higher frequency clocksignal.
 22. The method of claim 20, wherein the second higher frequencyclock signal is selectively output independent of the first higherfrequency clock signal, and wherein the second higher frequency clocksignal is selectively output by being output as is or reduced accordingto the power mode signal.
 23. The method of claim 20, wherein the secondhigher frequency clock signal has at least two different frequenciesselected in accordance with the power mode signal.
 24. A method forperforming clock speed generation, comprising: supplying a first clocksignal by a first logic to generate a first higher frequency clocksignal to a CPU; supplying a second clock signal by a second logic togenerate a second higher frequency clock signal to a bridge controller,wherein the first and second clock signals are distinct; receiving bythe second logic, a power mode signal and adjusting the second clocksignal; and selectively outputting the second higher frequency clocksignal based on the power mode signal independent of the first clocksignal, wherein the bridge controller controls a clock speed of a busconnected therebetween for data communication with the CPU using theoutputted second higher frequency clock signal.
 25. The method of claim24, wherein the first clock signal is greater than the second clocksignal, wherein the power mode signal is an AC power mode signal orbattery power mode signal.
 26. The method of claim 24, wherein the firstlogic and the second logic are PLLs (Phase Locked Loop).
 27. A mobileterminal, comprising: a processing unit operating at a first clock and abridge controller provided with a second clock, each configured toprocess data, wherein the first and second clock signals are twodistinct clock signals and have different frequencies; and a videoprocessing unit configured to process video data and to operate at athird clock signal, wherein the third clock signal is distinct from thefirst and second clock signals and has a different frequency than atleast one of the first and second clock signals, and the frequency ofthe third clock signal is varied based on a power source.
 28. The mobileterminal of claim 27, wherein the power source is one of AC power modeand battery power mode.
 29. The mobile terminal of claim 27, wherein afrequency of the first clock signal of the processing unit is variedbased on the power source.
 30. The mobile terminal of claim 29, whereinthe power source is one of AC power mode and battery power mode.
 31. Themobile terminal of claim 30, wherein the frequency of the first clocksignal is varied such that the frequency of the first clock signal inthe AC power mode is higher than the frequency of the first clock signalin the battery power mode, and the frequency of the third clock signalis varied such that the frequency of the third clock signal in the ACpower mode is higher than the frequency of the third clock signal in thebattery power mode.
 32. The mobile terminal of claim 29, furthercomprising: a first phase locked loop (PLL) circuit configured to varythe frequency of the first clock signal based on the power source; asecond PLL circuit configured to control the second clock signal; and athird PLL circuit configured to vary the frequency of the third clocksignal based on the power source.
 33. The mobile terminal of clam 32,wherein the first, second and third PPL circuits are provided in theprocessing unit, the bridge controller, and the video processing unit,respectively.
 34. A mobile terminal, comprising: a processing unithaving a first phase locked loop (PLL) circuit and configured to operateat a first clock; a bridge controller having a second PLL circuit andconfigured to operate at a second clock; a video processing unit havinga third PLL circuit and configured to operate at a third clock, whereina frequency of the first clock of the processing unit is varied based ona power source, and a frequency of the third clock of the videoprocessing unit is varied based on the power source.
 35. The mobileterminal of claim 34, wherein the power source is one of AC power modeand battery power mode.
 36. The mobile terminal of claim 35, wherein thefrequency of the first clock is varied such that the frequency of thefirst clock in the AC power mode is higher than the frequency of thefirst clock in the battery power mode, and the frequency of the thirdclock is varied such that the frequency of the third clock in the ACpower mode is higher than the frequency of the third clock in thebattery power mode.
 37. The mobile terminal of claim 36, wherein thebridge controller controls a clock speed of a bus connected between theprocessing unit and the bridge controller for data communication among aplurality of peripheral devices of the mobile terminal using the secondclock.
 38. A method of controlling a mobile terminal including aprocessing unit, a bridge controller and a video processing unit, alloperatively coupled, the method comprising: generating a first clock forthe processing unit, a second clock for the bridge controller, and athird clock for the video processing unit, wherein the first, second andthird clocks are distinct clocks and have different frequencies; varyinga frequency of the first clock based on a power mode of the mobileterminal and operating the processing unit at the varied first clock;and varying a frequency of the third clock based on the power mode ofthe mobile terminal and operating the video processing unit at thevaried third clock.
 39. The method of claim 38, wherein the power sourceis one of AC power mode and battery power mode.
 40. The method of claim39, wherein the frequency of the first clock is varied such that thefrequency of the first clock in the AC power mode is higher than thefrequency of the first clock in the battery power mode, and thefrequency of the third clock is varied such that the frequency of thethird clock in the AC power mode is higher than the frequency of thethird clock in the battery power mode.
 41. The method of claim 40,further comprising: controlling, by the bridge controller, a clock speedof a bus connected between the processing unit and the bridge controllerfor data communication among a plurality of peripheral devices of themobile terminal, using the second clock.
 42. A method for performingclock speed generation, comprising: supplying a first clock signal by afirst logic to generate a first higher frequency clock signal for aprocessing unit; supplying a second clock signal for a bridgecontroller, wherein the first and second clock signals are distinct, andthe bridge controller controls a clock speed of a bus connectedtherebetween for data communication with the processing unit using thesecond clock signal; supplying a third clock signal by a third logic togenerate a third higher frequency clock signal for a video processingunit; and selectively outputting the third higher frequency clock signalbased on a power mode signal.
 43. The method of claim 42, wherein thepower mode signal is an AC power mode signal or battery power modesignal.
 44. The method of claim 42, wherein the first logic and thesecond logic are PLLs (Phase Locked Loop).
 45. The method of claim 42,further comprising: selectively outputting the first higher frequencyclock signal based on the power mode signal.